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3.17.13 MIPS Options

These `-m' options are defined for the MIPS family of computers:

Generate code that will run on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: `mips1', `mips2', `mips3', `mips4', `mips32' and `mips64'. The processor names are: `r2000', `r3000', `r3900', `r4000', `vr4100', `vr4300', `r4400', `r4600', `r4650', `vr5000', `r6000', `r8000', `4kc', `4kp', `5kc', `20kc', `orion', and `sb1'. The special value `from-abi' selects the most compatible architecture for the selected ABI (that is, `mips1' for 32-bit ABIs and `mips3' for 64-bit ABIs).

In processor names, a final `000' can be abbreviated as `k' (for example, `-march=r2k'). Prefixes are optional, and `vr' may be written `r'.

GCC defines two macros based on the value of this option. The first is `_MIPS_ARCH', which gives the name of target architecture, as a string. The second has the form `_MIPS_ARCH_foo', where foo is the capitalized value of `_MIPS_ARCH'. For example, `-march=r2000' will set `_MIPS_ARCH' to `"r2000"' and define the macro `_MIPS_ARCH_R2000'.

Note that the `_MIPS_ARCH' macro uses the processor names given above. In other words, it will have the full prefix and will not abbreviate `000' as `k'. In the case of `from-abi', the macro names the resolved architecture (either `"mips1"' or `"mips3"'). It names the default architecture when no -march option is given.

Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.

When this option is not used, GCC will optimize for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that will run on a family of processors, but optimize the code for one particular member of that family.

`-mtune' defines the macros `_MIPS_TUNE' and `_MIPS_TUNE_foo', which work in the same way as the `-march' ones described above.

Equivalent to `-march=mips1'.
Equivalent to `-march=mips2'.
Equivalent to `-march=mips3'.
Equivalent to `-march=mips4'.
Equivalent to `-march=mips32'.
Equivalent to `-march=mips64'.
Generate code that uses (does not use) the floating point multiply and accumulate instructions, when they are available. These instructions are generated by default if they are available, but this may be undesirable if the extra precision causes problems or on certain chips in the mode where denormals are rounded to zero where denormals generated by multiply and accumulate instructions cause exceptions anyway.
Assume that floating point registers are 32 bits wide.
Assume that floating point registers are 64 bits wide.
Assume that general purpose registers are 32 bits wide.
Assume that general purpose registers are 64 bits wide.
Force int and long types to be 64 bits wide. See -mlong32 for an explanation of the default, and the width of pointers.
Force long types to be 64 bits wide. See -mlong32 for an explanation of the default, and the width of pointers.
Force long, int, and pointer types to be 32 bits wide.

The default size of ints, longs and pointers depends on the ABI. All the supported ABIs use 32-bit ints. The n64 ABI uses 64-bit longs, as does the 64-bit Cygnus EABI; the others use 32-bit longs. Pointers are the same size as longs, or the same size as integer registers, whichever is smaller.

Generate code for the given ABI.

Note that there are two embedded ABIs: -mabi=eabi selects the one defined by Cygnus while -meabi=meabi selects the one defined by MIPS. Both these ABIs have 32-bit and 64-bit variants. Normally, GCC will generate 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.

Generate code for the MIPS assembler, and invoke mips-tfile to add normal debug information. This is the default for all platforms except for the OSF/1 reference platform, using the OSF/rose object format. If the either of the -gstabs or -gstabs+ switches are used, the mips-tfile program will encapsulate the stabs within MIPS ECOFF.
Generate code for the GNU assembler. This is the default on the OSF/1 reference platform, using the OSF/rose object format. Also, this is the default if the configure option --with-gnu-as is used.
Generate code to load the high and low parts of address constants separately. This allows GCC to optimize away redundant loads of the high order bits of addresses. This optimization requires GNU as and GNU ld. This optimization is enabled by default for some embedded targets where GNU as and GNU ld are standard.
The -mrnames switch says to output code using the MIPS software names for the registers, instead of the hardware names (ie, a0 instead of $4). The only known assembler that supports this option is the Algorithmics assembler.
The -mgpopt switch says to write all of the data declarations before the instructions in the text section, this allows the MIPS assembler to generate one word memory references instead of using two words for short global or static data items. This is on by default if optimization is selected.
For each non-inline function processed, the -mstats switch causes the compiler to emit one line to the standard error file to print statistics about the program (number of registers saved, stack size, etc.).
The -mmemcpy switch makes all block moves call the appropriate string function (`memcpy' or `bcopy') instead of possibly generating inline code.
The -mno-mips-tfile switch causes the compiler not postprocess the object file with the mips-tfile program, after the MIPS assembler has generated it to add debug support. If mips-tfile is not run, then no local variables will be available to the debugger. In addition, stage2 and stage3 objects will have the temporary file names passed to the assembler embedded in the object file, which means the objects will not compare the same. The -mno-mips-tfile switch should only be used when there are bugs in the mips-tfile program that prevents compilation.
Generate output containing library calls for floating point. Warning: the requisite libraries are not part of GCC. Normally the facilities of the machine's usual C compiler are used, but this can't be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.
Generate output containing floating point instructions. This is the default if you use the unmodified sources.
Emit (or do not emit) the pseudo operations `.abicalls', `.cpload', and `.cprestore' that some System V.4 ports use for position independent code.
Do all calls with the `JALR' instruction, which requires loading up a function's address into a register before the call. You need to use this switch, if you call outside of the current 512 megabyte segment to functions that are not through pointers.
Put pointers to extern references into the data section and load them up, rather than put the references in the text section.
Generate PIC code suitable for some embedded systems. All calls are made using PC relative address, and all data is addressed using the $gp register. No more than 65536 bytes of global data may be used. This requires GNU as and GNU ld which do most of the work. This currently only works on targets which use ECOFF; it does not work with ELF.
Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
When used together with -membedded-data, it will always store uninitialized const variables in the read-only data section.
The -msingle-float switch tells gcc to assume that the floating point coprocessor only supports single precision operations, as on the `r4650' chip. The -mdouble-float switch permits gcc to use double precision operations. This is the default.
Permit use of the `mad', `madu' and `mul' instructions, as on the `r4650' chip.
Turns on -msingle-float, -mmad, and, at least for now, -mcpu=r4650.
Enable 16-bit instructions.
Use the entry and exit pseudo ops. This option can only be used with -mips16.
Compile code for the processor in little endian mode. The requisite libraries are assumed to exist.
Compile code for the processor in big endian mode. The requisite libraries are assumed to exist.
-G num
Put global and static items less than or equal to num bytes into the small data or bss sections instead of the normal data or bss section. This allows the assembler to emit one word memory reference instructions based on the global pointer (gp or $28), instead of the normal two words used. By default, num is 8 when the MIPS assembler is used, and 0 when the GNU assembler is used. The -G num switch is also passed to the assembler and linker. All modules should be compiled with the same -G num value.
Tell the MIPS assembler to not run its preprocessor over user assembler files (with a `.s' suffix) when assembling them.
Pass an option to gas which will cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
Do not include the default crt0.
Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common _flush_func(), that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target gcc was configured for, but commonly is either `_flush_func' or `__cpu_flush'.
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors which implement those architectures; for those, Branch Likely instructions will not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.