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3.17.22 MIPS Options

Generate big-endian code.
Generate little-endian code. This is the default for `mips*el-*-*' configurations.
Generate code that will run on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: `mips1', `mips2', `mips3', `mips4', `mips32', `mips32r2', `mips64' and `mips64r2'. The processor names are: `4kc', `4km', `4kp', `4ksc', `4kec', `4kem', `4kep', `4ksd', `5kc', `5kf', `20kc', `24kc', `24kf2_1', `24kf1_1', `24kec', `24kef2_1', `24kef1_1', `34kc', `34kf2_1', `34kf1_1', `74kc', `74kf2_1', `74kf1_1', `74kf3_2', `loongson2e', `loongson2f', `m4k', `octeon', `orion', `r2000', `r3000', `r3900', `r4000', `r4400', `r4600', `r4650', `r6000', `r8000', `rm7000', `rm9000', `r10000', `r12000', `r14000', `r16000', `sb1', `sr71000', `vr4100', `vr4111', `vr4120', `vr4130', `vr4300', `vr5000', `vr5400', `vr5500' and `xlr'. The special value `from-abi' selects the most compatible architecture for the selected ABI (that is, `mips1' for 32-bit ABIs and `mips3' for 64-bit ABIs).

Native Linux/GNU toolchains also support the value `native', which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.

In processor names, a final `000' can be abbreviated as `k' (for example, `-march=r2k'). Prefixes are optional, and `vr' may be written `r'.

Names of the form `nf2_1' refer to processors with FPUs clocked at half the rate of the core, names of the form `nf1_1' refer to processors with FPUs clocked at the same rate as the core, and names of the form `nf3_2' refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, `nf' is accepted as a synonym for `nf2_1' while `nx' and `bfx' are accepted as synonyms for `nf1_1'.

GCC defines two macros based on the value of this option. The first is `_MIPS_ARCH', which gives the name of target architecture, as a string. The second has the form `_MIPS_ARCH_foo', where foo is the capitalized value of `_MIPS_ARCH'. For example, `-march=r2000' will set `_MIPS_ARCH' to `"r2000"' and define the macro `_MIPS_ARCH_R2000'.

Note that the `_MIPS_ARCH' macro uses the processor names given above. In other words, it will have the full prefix and will not abbreviate `000' as `k'. In the case of `from-abi', the macro names the resolved architecture (either `"mips1"' or `"mips3"'). It names the default architecture when no -march option is given.

Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.

When this option is not used, GCC will optimize for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that will run on a family of processors, but optimize the code for one particular member of that family.

`-mtune' defines the macros `_MIPS_TUNE' and `_MIPS_TUNE_foo', which work in the same way as the `-march' ones described above.

Equivalent to `-march=mips1'.
Equivalent to `-march=mips2'.
Equivalent to `-march=mips3'.
Equivalent to `-march=mips4'.
Equivalent to `-march=mips32'.
Equivalent to `-march=mips32r2'.
Equivalent to `-march=mips64'.
Equivalent to `-march=mips64r2'.
Generate (do not generate) MIPS16 code. If GCC is targetting a MIPS32 or MIPS64 architecture, it will make use of the MIPS16e ASE.

MIPS16 code generation can also be controlled on a per-function basis by means of mips16 and nomips16 attributes. See Function Attributes, for more information.

Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code.
Require (do not require) that non-MIPS16 code be link-compatible with MIPS16 code.

For example, non-MIPS16 code cannot jump directly to MIPS16 code; it must either use a call or an indirect jump. -minterlink-mips16 therefore disables direct jumps unless GCC knows that the target of the jump is not MIPS16.

Generate code for the given ABI.

Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.

For information about the O64 ABI, see

GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with -mabi=32 -mfp64. This ABI relies on the `mthc1' and `mfhc1' instructions and is therefore only supported for MIPS32R2 processors.

The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in `$f0' only, not a `$f0'/`$f1' pair. The set of call-saved registers also remains the same, but all 64 bits are saved.

Generate (do not generate) code that is suitable for SVR4-style dynamic objects. -mabicalls is the default for SVR4-based systems.
Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects -mabicalls.

All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by -mno-shared.

-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using -mno-shared will generally make executables both smaller and quicker.

-mshared is the default.

Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects `-mno-shared -mabicalls'. For the n64 ABI, this option has no effect without `-msym32'.

You can make -mplt the default by configuring GCC with --with-mips-plt. The default is -mno-plt otherwise.

Lift (do not lift) the usual restrictions on the size of the global offset table.

GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it will only work if the GOT is smaller than about 64k. Anything larger will cause the linker to report an error such as:

          relocation truncated to fit: R_MIPS_GOT16 foobar

If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs, although it will also be less efficient, since it will take three instructions to fetch the value of a global symbol.

Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do.

These options have no effect unless GCC is generating position independent code.

Assume that general-purpose registers are 32 bits wide.
Assume that general-purpose registers are 64 bits wide.
Assume that floating-point registers are 32 bits wide.
Assume that floating-point registers are 64 bits wide.
Use floating-point coprocessor instructions.
Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead.
Assume that the floating-point coprocessor only supports single-precision operations.
Assume that the floating-point coprocessor supports double-precision operations. This is the default.
Use (do not use) `ll', `sc', and `sync' instructions to implement atomic memory built-in functions. When neither option is specified, GCC will use the instructions if the target architecture supports them.

-mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with --with-llsc and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation documentation for details.

Use (do not use) revision 1 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines the preprocessor macro `__mips_dsp'. It also defines `__mips_dsp_rev' to 1.
Use (do not use) revision 2 of the MIPS DSP ASE. See MIPS DSP Built-in Functions. This option defines the preprocessor macros `__mips_dsp' and `__mips_dspr2'. It also defines `__mips_dsp_rev' to 2.
Use (do not use) the MIPS SmartMIPS ASE.
Use (do not use) paired-single floating-point instructions. See MIPS Paired-Single Support. This option requires hardware floating-point support to be enabled.
Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
Use (do not use) the MIPS-3D ASE. See MIPS-3D Built-in Functions. The option -mips3d implies -mpaired-single.
Use (do not use) MT Multithreading instructions.
Force long types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
Force long, int, and pointer types to be 32 bits wide.

The default size of ints, longs and pointers depends on the ABI. All the supported ABIs use 32-bit ints. The n64 ABI uses 64-bit longs, as does the 64-bit EABI; the others use 32-bit longs. Pointers are the same size as longs, or the same size as integer registers, whichever is smaller.

Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
-G num
Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes. GCC can then access the data more efficiently; see -mgpopt for details.

The default -G option depends on the configuration.

Extend (do not extend) the -G behavior to local data too, such as to static variables in C. -mlocal-sdata is the default for all configurations.

If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with -mno-local-sdata. You might also want to build large libraries with -mno-local-sdata, so that the libraries leave more room for the main program.

Assume (do not assume) that externally-defined data will be in a small data section if that data is within the -G limit. -mextern-sdata is the default for all configurations.

If you compile a module Mod with -mextern-sdata -G num -mgpopt, and Mod references a variable Var that is no bigger than num bytes, you must make sure that Var is placed in a small data section. If Var is defined by another module, you must either compile that module with a high-enough -G setting or attach a section attribute to Var's definition. If Var is common, you must link the application with a high-enough -G setting.

The easiest way of satisfying these restrictions is to compile and link every module with the same -G option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported -G setting and additionally using -mno-extern-sdata to stop the library from making assumptions about externally-defined data.

Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations.

-mno-gpopt is useful for cases where the $gp register might not hold the value of _gp. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines will pass an unknown value in $gp. (In such situations, the boot monitor itself would usually be compiled with -G0.)

-mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.

Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
Put uninitialized const variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
Specify whether GCC may generate code that reads from executable sections. There are three possible settings:
Instructions may freely access executable sections. This is the default setting.
MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM.
Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM.

Enable (disable) use of the %hi() and %lo() assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.

-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.

Trap (do not trap) on integer division by zero.

The default is -mcheck-zero-division.

MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (SIGFPE). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.

The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division.

Force (do not force) the use of memcpy() for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant-sized copies.
Disable (do not disable) use of the jal instruction. Calling functions using jal is more efficient but requires the caller and callee to be in the same 256 megabyte segment.

This option has no effect on abicalls code. The default is -mno-long-calls.

Enable (disable) use of the mad, madu and mul instructions, as provided by the R4650 ISA.
Enable (disable) use of the floating point multiply-accumulate instructions, when they are available. The default is -mfused-madd.

When multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances.

Tell the MIPS assembler to not run its preprocessor over user assembler files (with a `.s' suffix) when assembling them.
Work around certain R4000 CPU errata:
Work around certain R4400 CPU errata:
Work around certain R10000 errata:

This option can only be used if the target architecture supports branch-likely instructions. -mfix-r10000 is the default when -march=r10000 is used; -mno-fix-r10000 is the default otherwise.

Work around certain VR4120 errata: The workarounds for the division errata rely on special functions in libgcc.a. At present, these functions are only provided by the mips64vr*-elf configurations.

Other VR4120 errata require a nop to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.

Work around the VR4130 mflo/mfhi errata. The workarounds are implemented by the assembler rather than by GCC, although GCC will avoid using mflo and mfhi if the VR4130 macc, macchi, dmacc and dmacchi instructions are available instead.
Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 “F1” and “F2” floating point errata.)
Specify whether GCC should insert cache barriers to avoid the side-effects of speculation on R10K processors.

In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the “taken” branch. It later aborts these instructions if the predicted outcome was wrong. However, on the R10K, even aborted instructions can have side effects.

This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the “dirty” line is flushed, the cached data will overwrite the DMA-ed data. See the R10K processor manual for a full description, including other potential problems.

One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier=setting controls GCC's implementation of this workaround. It assumes that aborted accesses to any byte in the following regions will not have side effects:

  1. the memory occupied by the current function's stack frame;
  2. the memory occupied by an incoming stack argument;
  3. the memory occupied by an object with a link-time-constant address.

It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe.

If the input program contains a function declaration such as:

          void foo (void);

then the implementation of foo must allow j foo and jal foo to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same.

The option has three forms:

Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted.
Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted.
Disable the insertion of cache barriers. This is the default setting.

Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common _flush_func(), that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either `_flush_func' or `__cpu_flush'.
Set the cost of branches to roughly num “simple” instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the -mtune setting.
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors which implement those architectures; for those, Branch Likely instructions will not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
Specifies whether FP exceptions are enabled. This affects how we schedule FP instructions for some processors. The default is that FP exceptions are enabled.

For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.

The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC will align pairs of instructions that it thinks should execute in parallel.

This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.