The macros in this section can be split in two families, according to the two ways of representing condition codes in GCC.
The first representation is the so called (cc0) representation
(see Jump Patterns), where all instructions can have an implicit
clobber of the condition codes. The second is the condition code
register representation, which provides better schedulability for
architectures that do have a condition code register, but on which
most instructions do not affect it. The latter category includes
most RISC machines.
The implicit clobbering poses a strong restriction on the placement of
the definition and use of the condition code. In the past the definition
and use were always adjacent. However, recent changes to support trapping
arithmatic may result in the definition and user being in different blocks.
Thus, there may be a NOTE_INSN_BASIC_BLOCK between them. Additionally,
the definition may be the source of exception handling edges.
These restrictions can prevent important optimizations on some machines. For example, on the IBM RS/6000, there is a delay for taken branches unless the condition code register is set three instructions earlier than the conditional branch. The instruction scheduler cannot perform this optimization if it is not permitted to separate the definition and use of the condition code register.
For this reason, it is possible and suggested to use a register to
represent the condition code for new ports. If there is a specific
condition code register in the machine, use a hard register. If the
condition code or comparison result can be placed in any general register,
or if there are multiple condition registers, use a pseudo register.
Registers used to store the condition code value will usually have a mode
that is in class MODE_CC.
Alternatively, you can use BImode if the comparison operator is
specified already in the compare instruction. In this case, you are not
interested in most macros in this section.