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3.18.37 RISC-V Options

These command-line options are defined for RISC-V targets:


Set the cost of branches to roughly n instructions.


Don’t optimize block moves.


When generating PIC code, allow the use of PLTs. Ignored for non-PIC.


Specify integer and floating-point calling convention. This defaults to the natural calling convention: e.g. LP64 for RV64I, ILP32 for RV32I, LP64D for RV64G.


Use hardware floating-point divide and square root instructions. This requires the F or D extensions for floating-point registers.


Use hardware instructions for integer division. This requires the M extension.


Generate code for given RISC-V ISA (e.g. ‘rv64im’). ISA strings must be lower-case. Examples include ‘rv64i’, ‘rv32g’, and ‘rv32imaf’.


Optimize the output for the given processor, specified by microarchitecture name.


Put global and static data smaller than n bytes into a special section (on some targets).


Use smaller but slower prologue and epilogue code.


Specify the code model.