Target uses big-endian memory order for multi-byte and multi-word data.

Target uses little-endian memory order for multi-byte and multi-word data.

Target has 32-bit int, long, and pointers.

Target has 32-bit int, 64-bit long and pointers.

Target has 32-bit int and long, 64-bit long long and pointers.

Target has 64-bit double.

Target has double that is 64 bits or longer.

Target has 128-bit long double.

Target has int that is at 32 bits or longer.

Target has int that is 16 bits or shorter.

Target has 64-bit long long.

Target has int and long with different sizes.

Target has short and int with the same size.

Target has pointers (void *) and short with the same size.

Target has int and float with the same size.

Target has pointers (void *) and long with the same size.

Target supports double that is longer than float.

Target supports long double that is longer than double.

Target has pointers that are 32 bits or longer.

Target has a 20-bit or larger address space, so supports at least 16-bit array and structure sizes.

Target has a 24-bit or larger address space, so supports at least 20-bit array and structure sizes.

Target has a 32-bit or larger address space, so supports at least 24-bit array and structure sizes.

Target has wchar_t that is at least 4 bytes.

Target has the _Floatn type.

Target has the _Floatnx type.

Target has the _Floatn type, including runtime support for any options added with dg-add-options.

Target has the _Floatnx type, including runtime support for any options added with dg-add-options.

Target has runtime support for any options added with dg-add-options for any _Floatn or _Floatnx type.

Target supports floating point infinite (inf) for type double.

Target supports floating point infinite (inf) for type float.

Target supports Fortran integer that is 16 bytes or longer.

Target supports Fortran real that is 10 bytes or longer.

Target supports Fortran real that is 16 bytes or longer.

Target supports Fortran integer kinds larger than integer(8).

Target supports Fortran real kinds larger than real(8).

The target’s ABI allows stack variables to be aligned to the preferred vector alignment.

Target supports both signed and unsigned averaging operations on vectors of bytes.

Target supports both signed and unsigned multiply-high-with-round-and-scale operations on vectors of half-words.

Target supports signed division by constant power-of-2 operations on vectors of 4-byte integers.

Target supports vector conditional operations.

Target supports vector conditional operations where comparison operands have different type from the value operands.

Target supports hardware vectors of double.

Target supports conditional addition, subtraction, multiplication, division, minimum and maximum on vectors of double, via the cond_ optabs.

The target’s preferred vector alignment is the same as the element alignment.

Target supports hardware vectors of float when -funsafe-math-optimizations is in effect.

Target supports hardware vectors of float when -funsafe-math-optimizations is not in effect. This implies vect_float.

Target supports hardware vectors of int.

Target supports hardware vectors of long.

Target supports hardware vectors of long long.

Target supports the check_raw_ptrs and check_war_ptrs optabs on vectors.

Target supports fully-masked (also known as fully-predicated) loops, so that vector loops can handle partial as well as full vectors.

Target supports vector masked loads.

Target supports vector masked stores.

Target supports vector gather loads using internal functions (rather than via built-in functions or emulation).

Target supports vector scatter stores.

Target aligns arrays to vector alignment boundary.

Target supports a vector misalign access.

Target does not support a vector alignment mechanism.

Target might require to peel loops for alignment purposes.

Target does not support a vector min and max instruction on int.

Target does not support a vector add instruction on int.

Target does not support vector bitwise instructions.

Target supports comparison of bool vectors for at least one vector length.

Target supports addition of char vectors for at least one vector length.

Target supports vector char multiplication.

Target supports vector short multiplication.

Target supports vector int multiplication.

Target supports 64 bit vector long multiplication.

Target supports vector even/odd element extraction.

Target supports vector even/odd element extraction of vectors with elements SImode or larger.

Target supports vector interleaving.

Target supports vector interleaving and extract even/odd.

Target supports vector interleaving and extract even/odd for wide element types.

Target supports vector permutation.

Target supports permutation of vectors with 8-bit elements.

Target supports permutation of vectors with 16-bit elements.

Target supports permutation of vectors with 8-bit elements, and for the default vector length it is possible to permute:

{ a0, a1, a2, b0, b1, b2, … }

to:

{ a0, a0, a0, b0, b0, b0, … }
{ a1, a1, a1, b1, b1, b1, … }
{ a2, a2, a2, b2, b2, b2, … }

using only two-vector permutes, regardless of how long the sequence is.

Like vect_perm3_byte, but for 32-bit elements.

Like vect_perm3_byte, but for 16-bit elements.

Target supports a hardware vector shift operation.

Target prefers vectors to have an alignment greater than element alignment, but also allows unaligned vector accesses in some circumstances.

Target has variable-length vectors.

Target supports vectors of 64 bits.

Target supports vectors of 32 bits.

Target supports a vector widening summation of short operands into int results, or can promote (unpack) from short to int.

Target supports a vector widening summation of char operands into short results, or can promote (unpack) from char to short.

Target supports a vector widening summation of char operands into int results.

Target supports a vector widening multiplication of char operands into short results, or can promote (unpack) from char to short and perform non-widening multiplication of short.

Target supports a vector widening multiplication of short operands into int results, or can promote (unpack) from short to int and perform non-widening multiplication of int.

Target supports a vector widening multiplication of int operands into long results.

Target supports a vector dot-product of signed char.

Target supports a vector dot-product of unsigned char.

Target supports a vector dot-product where one operand of the multiply is signed char and the other of unsigned char.

Target supports a vector dot-product of signed short.

Target supports a vector dot-product of unsigned short.

Target supports a vector demotion (packing) of short to char and from int to short using modulo arithmetic.

Target supports a vector promotion (unpacking) of char to short and from char to int.

Target supports conversion from signed int to float.

Target supports conversion from unsigned int to float.

Target supports conversion from float to signed int.

Target supports conversion from float to unsigned int.

Target supports conversion from signed int to double.

Target supports conversion from double to signed int.

Target supports max reduction for vectors.

Target supports 16- and 8-bytes vectors.

Target supports 32- and 16-bytes vectors.

Target supports AND, IOR and XOR reduction on vectors.

Target supports the fold_extract_last optab.

Target supports the len_load and len_store optabs.

Target supports loop vectorization with partial vectors and vect-partial-vector-usage is set to 1.

Target supports loop vectorization with partial vectors and vect-partial-vector-usage is set to 2.

Target supports loop vectorization with partial vectors and vect-partial-vector-usage is nonzero.

Target supports vectorization of 2-byte char stores with 2-byte aligned address at plain -O2.

Target supports vectorization of 4-byte char stores with 4-byte aligned address at plain -O2.

Target supports vectorization of 4-byte char stores with unaligned address at plain -O2.

Target supports block move for 8-byte aligned 4-byte size struct initialization.

Target supports vectorization of 4-byte char stores with unaligned address or store them with constant pool at plain -O2.

Target supports block move for 8-byte aligned 8-byte size struct initialization.

Target supports vectorization of 8-byte char stores with unaligned address or store them with constant pool at plain -O2.

Target supports block move for 8-byte aligned 16-byte size struct initialization.

Target supports vectorization of 16-byte char stores with unaligned address or store them with constant pool at plain -O2.

Target supports vectorization of 4-byte short stores with 4-byte aligned addressat plain -O2.

Target supports vectorization of 4-byte short stores with unaligned address at plain -O2.

Target supports vectorization of 8-byte short stores with unaligned address at plain -O2.

Target supports vectorization of 8-byte int stores with 8-byte aligned address at plain -O2.

Target supports vectorization of 16-byte int stores with unaligned address at plain -O2.

Target supports thread-local storage.

Target supports native (rather than emulated) thread-local storage.

Test system supports executing TLS executables.

Targets supports compiling decimal floating point extension to C.

Including the options used to compile this particular test, the target supports compiling decimal floating point extension to C.

Test system can execute decimal floating point tests.

Including the options used to compile this particular test, the test system can execute decimal floating point tests.

Target generates decimal floating point instructions with current options.

ARM target generates 32-bit code.

ARM target that generates little-endian code.

ARM target adheres to the ABI for the ARM Architecture.

ARM target defines __ARM_FP using -mfloat-abi=softfp or equivalent options. Some multilibs may be incompatible with these options.

ARM target defines __ARM_FP with double-precision support using -mfloat-abi=softfp or equivalent options. Some multilibs may be incompatible with these options.

ARM target adheres to the VFP and Advanced SIMD Register Arguments variant of the ABI for the ARM Architecture (as selected with -mfloat-abi=hard).

ARM target uses emulated floating point operations.

ARM target supports -mfpu=vfp -mfloat-abi=hard. Some multilibs may be incompatible with these options.

ARM target supports -mcpu=iwmmxt. Some multilibs may be incompatible with this option.

ARM target supports generating NEON instructions.

Test CPU tune supports inlining string operations with NEON instructions.

Test system supports executing NEON instructions.

Test system supports executing NEON v2 instructions.

ARM Target supports -mfpu=neon -mfloat-abi=softfp or compatible options. Some multilibs may be incompatible with these options.

ARM Target supports NEON with -mfpu=neon, but without any -mfloat-abi= option. Some multilibs may be incompatible with this option.

ARM Target supports -mfpu=neon-vfpv4 -mfloat-abi=softfp or compatible options. Some multilibs may be incompatible with these options.

Target supports options to generate VFP half-precision floating-point instructions. Some multilibs may be incompatible with these options. This test is valid for ARM only.

Target supports executing VFP half-precision floating-point instructions. This test is valid for ARM only.

ARM Target supports -mfpu=neon-fp16 -mfloat-abi=softfp or compatible options, including -mfp16-format=ieee if necessary to obtain the __fp16 type. Some multilibs may be incompatible with these options.

Test system supports executing Neon half-precision float instructions. (Implies previous.)

ARM target supports the ARM FP16 alternative format. Some multilibs may be incompatible with the options needed.

ARM target supports specifying none as the ARM FP16 format.

ARM target generates Thumb-1 code for -mthumb.

ARM target generates Thumb-2 code for -mthumb.

ARM target that is not using Thumb.

ARM target supports -mfpu=vfp -mfloat-abi=softfp. Some multilibs may be incompatible with these options.

ARM target supports -mfpu=vfp3 -mfloat-abi=softfp. Some multilibs may be incompatible with these options.

The compiler is targeting arm*-*-* and can compile and assemble code using the options -march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard. This is not enough to guarantee that linking works.

The compiler is targeting arm*-*-* and can build programs using the options -march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard. The target can also run the resulting binaries.

ARM target supports -mfpu=fp-armv8 -mfloat-abi=softfp. Some multilibs may be incompatible with these options.

ARM target supports -mfpu=neon-fp-armv8 -mfloat-abi=softfp. Some multilibs may be incompatible with these options.

ARM target supports options to generate ARMv8.1-A Adv.SIMD instructions. Some multilibs may be incompatible with these options.

ARM target supports executing ARMv8.1-A Adv.SIMD instructions. Some multilibs may be incompatible with the options needed. Implies arm_v8_1a_neon_ok.

ARM target supports acquire-release instructions.

ARM target supports options to generate instructions for ARMv8.2-A and scalar instructions from the FP16 extension. Some multilibs may be incompatible with these options.

ARM target supports executing instructions for ARMv8.2-A and scalar instructions from the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_neon_ok.

ARM target supports options to generate instructions from ARMv8.2-A with the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_scalar_ok.

ARM target supports executing instructions from ARMv8.2-A with the FP16 extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.

ARM target supports options to generate instructions from ARMv8.2-A with the Dot Product extension. Some multilibs may be incompatible with these options.

ARM target supports executing instructions from ARMv8.2-A with the Dot Product extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_dotprod_neon_ok.

ARM target supports executing instructions from ARMv8.2-A with the 8-bit Matrix Multiply extension. Some multilibs may be incompatible with these options. Implies arm_v8_2a_i8mm_ok.

ARM target supports extensions to generate the VFMAL and VFMLS half-precision floating-point instructions available from ARMv8.2-A and onwards. Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8.2-A with the BFloat16 extension (bf16). Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8.2-A with the 8-Bit Integer Matrix Multiply extension (i8mm). Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8.1-M with the M-Profile Vector Extension (MVE). Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8.1-M with the Half-precision floating-point instructions (HP), Floating-point Extension (FP) along with M-Profile Vector Extension (MVE). Some multilibs may be incompatible with these options.

Test system supports executing MVE instructions.

ARM target supports options to generate instructions from ARMv8-M with the Custom Datapath Extension (CDE). Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8-M with the Custom Datapath Extension (CDE) and floating-point (VFP). Some multilibs may be incompatible with these options.

ARM target supports options to generate instructions from ARMv8.1-M with the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE). Some multilibs may be incompatible with these options.

ARM target prefers LDRD and STRD instructions over LDM and STM instructions.

ARM target generates Thumb-1 code for -mthumb with MOVW and MOVT instructions available.

ARM target generates Thumb-1 code for -mthumb with CBZ and CBNZ instructions available.

ARM target for which divmod transform is disabled, if it supports hardware div instruction.

ARM target supports ARMv8-M Security Extensions, enabled by the -mcmse option.

Test system supports executing CMSE instructions.

ARM target supports the following coprocessor instructions: CDP, LDC, STC, MCR and MRC.

ARM target supports all the coprocessor instructions also listed as supported in arm_coproc1_ok in addition to the following: CDP2, LDC2, LDC2l, STC2, STC2l, MCR2 and MRC2.

ARM target supports all the coprocessor instructions also listed as supported in arm_coproc2_ok in addition the following: MCRR and MRRC.

ARM target supports all the coprocessor instructions also listed as supported in arm_coproc3_ok in addition the following: MCRR2 and MRRC2.

ARM Target supports options suitable for accessing the SIMD32 intrinsics from arm_acle.h. Some multilibs may be incompatible with these options.

ARM Target supports options suitable for accessing the saturation intrinsics from arm_acle.h. Some multilibs may be incompatible with these options.

ARM Target supports options suitable for accessing the DSP intrinsics from arm_acle.h. Some multilibs may be incompatible with these options.

ARM target supports the -mfloat-abi=softfp option.

ARM target supports the -mfloat-abi=hard option.

ARM target supports generating MVE instructions.

ARM Target supports executing the Armv8.1-M Mainline Low Overhead Loop instructions DLS and LE. Some multilibs may be incompatible with these options.

ARM target where Thumb-2 is used without options but does not support executing the Armv8.1-M Mainline Low Overhead Loop instructions DLS and LE.

ARM target generates Thumb-2 code for -mthumb but does not support executing the Armv8.1-M Mainline Low Overhead Loop instructions DLS and LE.

AArch64 assembler supports the architecture extension ext via the .arch_extension pseudo-op.

AArch64 target which generates instruction sequences for tiny memory model.

AArch64 target which generates instruction sequences for small memory model.

AArch64 target which generates instruction sequences for large memory model.

AArch64 target which generates instruction sequences for little endian.

AArch64 target which generates instruction sequences for big endian.

Binutils installed on test system supports relocation types required by -fpic for AArch64 small memory model.

AArch64 target that is able to generate and execute SVE code (regardless of whether it does so by default).

Like aarch64_sve_hw, but also test for an exact hardware vector length.

AArch64 target that is able to generate and execute armv8.3-a FJCVTZS instruction.

MIPS target supports 64-bit instructions.

MIPS target does not produce MIPS16 code.

MIPS target can generate MIPS16 code.

MIPS target is a Loongson-2E or -2F target using an ABI that supports the Loongson vector modes.

MIPS target supports -mmsa, MIPS SIMD Architecture (MSA).

MIPS target supports long double larger than double when using the new ABI.

MIPS target supports -mpaired-single.

MSP430 target has the small memory model enabled (-msmall).

MSP430 target has the large memory model enabled (-mlarge).

PowerPC target supports executing hardware DFP instructions.

PowerPC target supports executing VSX instructions (ISA 2.07).

Test system supports executing 64-bit instructions.

PowerPC target supports AltiVec.

PowerPC target supports -maltivec.

PowerPC target supports -meabi.

PowerPC target supports -mabi=elfv2.

PowerPC target supports floating-point registers.

PowerPC target supports hardware double-precision floating-point.

PowerPC target supports -mhtm

PowerPC target supports -mpower8-vector

PowerPC target supports the popcntb instruction, indicating that this target supports -mcpu=power5.

PowerPC target supports -mcpu=cell.

PowerPC target supports PowerPC SPE.

Including the options used to compile this particular test, the PowerPC target supports PowerPC SPE.

PowerPC target supports PowerPC SPU.

PowerPC target supports -mvsx.

Including the options used to compile this particular test, the PowerPC target supports PowerPC 405.

PowerPC target supports executing reciprocal estimate instructions.

PowerPC target supports executing AltiVec instructions.

PowerPC target supports executing VSX instructions (ISA 2.06).

PowerPC target pre-defines macro _ARCH_PWR5 which means the -mcpu setting is Power5 or later.

PowerPC target pre-defines macro _ARCH_PWR6 which means the -mcpu setting is Power6 or later.

PowerPC target pre-defines macro _ARCH_PWR7 which means the -mcpu setting is Power7 or later.

PowerPC target pre-defines macro _ARCH_PWR8 which means the -mcpu setting is Power8 or later.

PowerPC target pre-defines macro _ARCH_PWR9 which means the -mcpu setting is Power9 or later.

Target supports autoincrement/decrement addressing.

Target supports compiling avx instructions.

Target supports the execution of avx instructions.

Target supports compiling avx2 instructions.

Target supports the execution of avx2 instructions.

Target supports the execution of avxvnni instructions.

Target supports compiling avx512f instructions.

Target supports the execution of avx512f instructions.

Target supports the execution of avx512vp2intersect instructions.

Target supports the execution of amx-tile instructions.

Target supports the execution of amx-int8 instructions.

Target supports the execution of amx-bf16 instructions.

Test system can execute AltiVec and Cell PPU instructions.

Target uses a ColdFire FPU.

Target supporting hardware divmod insn or divmod libcall.

Target supporting hardware divmod insn or divmod libcall for SImode.

Target supports FPU instructions.

Target does not require strict alignment.

The x86-64 target linker supports PIE with copy reloc.

Target supports x86 rdrand instruction.

Target has a square root instruction that the compiler can generate.

Target supports compiling sse instructions.

Target supports the execution of sse instructions.

Target supports compiling sse2 instructions.

Target supports the execution of sse2 instructions.

Target supports atomic operations on char and short.

Target supports atomic operations on int and long.

Test environment appears to run executables on a simulator that accepts only EM_SPARC executables and chokes on EM_SPARC32PLUS or EM_SPARCV9 executables.

Target requires a command line argument to enable a SIMD instruction set.

Target supports the xorsign optab expansion.

The language for the compiler under test is C.

The language for the compiler under test is C++.

Target provides a full C99 runtime.

Target string.h and wchar.h headers provide C++ required overloads for strchr etc. functions.

Target provides the D runtime.

Target provides the D standard library (Phobos).

Target uses a dummy wcsftime function that always returns zero.

Target can truncate a file from a file descriptor, as used by libgfortran/io/unix.c:fd_truncate; i.e. ftruncate or chsize.

Target provides fenv.h include file.

Target supports fenv.h with all the standard IEEE exceptions and floating-point exceptions are raised by arithmetic operations.

Target supports fenv.h with all the standard IEEE exceptions and floating-point exceptions are raised by arithmetic operations for decimal floating point.

Target offers such file I/O library functions as fopen, fclose, tmpnam, and remove. This is a link-time requirement for the presence of the functions in the library; even if they fail at runtime, the requirement is still regarded as satisfied.

Target is ‘freestanding’ as defined in section 4 of the C99 standard. Effectively, it is a target which supports no extra headers or libraries other than what is considered essential.

Target supports gettimeofday.

Target supports constructors with initialization priority arguments.

Target has the basic signed and unsigned types in inttypes.h. This is for tests that GCC’s notions of these types agree with those in the header, as some systems have only inttypes.h.

Target might have errors of a few ULP in string to floating-point conversion functions and overflow is not always detected correctly by those functions.

Target provides mempcpy function.

Target supports mmap.

Target supports Newlib.

GCC was configured with --enable-newlib-nano-formatted-io, which reduces the code size of Newlib formatted I/O functions.

Target provides pow10 function.

Target can compile using pthread.h with no errors or warnings.

Target has pthread.h.

Expensive testcases (usually those that consume excessive amounts of CPU time) should be run on this target. This can be enabled by setting the GCC_TEST_RUN_EXPENSIVE environment variable to a non-empty string.

Test system runs executables on a simulator (i.e. slowly) rather than hardware (i.e. fast).

Target has signal.h.

Target supports the stabs debugging format.

Target has the basic signed and unsigned C types in stdint.h. This will be obsolete when GCC ensures a working stdint.h for all targets.

Target accepts the option -mbig-endian and stdint.h can be included without error when -mbig-endian is passed.

Target provides stpcpy function.

Target supports sysconf.

Target supports trampolines.

Target supports uClibc.

Target does not use a status wrapper.

Target is a VxWorks kernel.

Target is a VxWorks RTP.

Target supports wide characters.

Target supports the ’R’ flag in .section directive in assembly inputs.

Target supports automatic stack alignment.

Target supports -branch-cost=N.

Target uses __cxa_atexit.

Target has packed layout of structure members by default.

Target supports exceptions.

Target supports exceptions and they are enabled in the current testing configuration.

Target supports Graphite optimizations.

Target supports fixed-point extension to C.

Target supports OpenACC via -fopenacc.

Target supports OpenMP via -fopenmp.

Target supports -fpic and -fPIC.

Target supports -freorder-blocks-and-partition.

Target supports -fstack-protector.

Target uses GNU as.

Target supports --gc-sections.

Target uses GNU ld.

Target keeps null pointer checks, either due to the use of -fno-delete-null-pointer-checks or hardwired into the target.

Target is using an LLVM assembler and/or linker, instead of GNU Binutils.

Target supports local register allocator (LRA).

Compiler has been configured to support link-time optimization (LTO).

Compiler and linker support link-time optimization relocatable linking with -r and -flto options.

Target supports the naked function attribute.

Target supports named sections.

Target uses natural alignment (aligned to type size) for types of 32 bits or less.

Target uses natural alignment (aligned to type size) for types of 64 bits or less.

Target supports the noinit variable attribute.

Target does not generate PIC by default.

Target supports the ’o’ flag in .section directive in assembly inputs.

Target has been configured for OpenACC/OpenMP offloading on AMD GCN.

Target supports the persistent variable attribute.

Target generates PIE by default.

Target defines PCC_BITFIELD_TYPE_MATTERS.

Target supports -mpe-aligned-commons.

Target supports -pie, -fpie and -fPIE.

Target supports -rdynamic.

Target supports all four fused multiply-add optabs for both float and double. These optabs are: fma_optab, fms_optab, fnma_optab and fnms_optab.

Target supports section anchors.

Target defaults to short enums.

Target has limited stack size. The stack size limit can be obtained using the STACK_SIZE macro defined by dg-add-options feature stack_size.

Target supports -static.

Target supports statically linking ‘libgfortran’.

Target supports merging string constants at link time.

Target supports compiling and assembling UCN.

Including the options used to compile this particular test, the target supports compiling and assembling UCN.

Target does not guarantee that its STACK_BOUNDARY is greater than or equal to the required vector alignment.

Vector alignment is reachable for types of 32 bits or less.

Vector alignment is reachable for types of 64 bits or less.

Target supports wchar_t that is compatible with char16_t.

Target supports wchar_t that is compatible with char32_t.

Target uses comdat groups.

Target supports indirect calls, i.e. calls where the target is not constant.

Target supports -lgccjit, i.e. libgccjit.so can be linked into jit tests.

Optimizations are enabled (__OPTIMIZE__) per the current compiler flags.

Target supports compiling 3dnow instructions.

Target supports compiling aes instructions.

Target supports compiling fma4 instructions.

Target supports the -mfentry option that alters the position of profiling calls such that they precede the prologue.

Target supports attribute ms_hook_prologue.

Target supports compiling pclmul instructions.

Target supports compiling sse3 instructions.

Target supports compiling sse4 instructions.

Target supports compiling sse4a instructions.

Target supports compiling ssse3 instructions.

Target supports compiling vaes instructions.

Target supports compiling vpclmul instructions.

Target supports compiling xop instructions.

Always returns 0.

Always returns 1.