Here are the RTL expression types for describing access to machine registers and to main memory.
(reg:m n) ¶For small values of the integer n (those that are less than
FIRST_PSEUDO_REGISTER), this stands for a reference to machine
register number n: a hard register. For larger values of
n, it stands for a temporary value or pseudo register.
The compiler’s strategy is to generate code assuming an unlimited
number of such pseudo registers, and later convert them into hard
registers or into memory references.
m is the machine mode of the reference. It is necessary because machines can generally refer to each register in more than one mode. For example, a register may contain a full word but there may be instructions to refer to it as a half word or as a single byte, as well as instructions to refer to it as a floating point number of various precisions.
Even for a register that the machine can access in only one mode, the mode must always be specified.
The symbol FIRST_PSEUDO_REGISTER is defined by the machine
description, since the number of hard registers on the machine is an
invariant characteristic of the machine. Note, however, that not
all of the machine registers must be general registers. All the
machine registers that can be used for storage of data are given
hard register numbers, even those that can be used only in certain
instructions or can hold only certain types of data.
A hard register may be accessed in various modes throughout one
function, but each pseudo register is given a natural mode
and is accessed only in that mode. When it is necessary to describe
an access to a pseudo register using a nonnatural mode, a subreg
expression is used.
A reg expression with a machine mode that specifies more than
one word of data may actually stand for several consecutive registers.
If in addition the register number specifies a hardware register, then
it actually represents several consecutive hardware registers starting
with the specified one.
Each pseudo register number used in a function’s RTL code is
represented by a unique reg expression.
Some pseudo register numbers, those within the range of
FIRST_VIRTUAL_REGISTER to LAST_VIRTUAL_REGISTER only
appear during the RTL generation phase and are eliminated before the
optimization phases. These represent locations in the stack frame that
cannot be determined until RTL generation for the function has been
completed. The following virtual register numbers are defined:
VIRTUAL_INCOMING_ARGS_REGNUM ¶This points to the first word of the incoming arguments passed on the stack. Normally these arguments are placed there by the caller, but the callee may have pushed some arguments that were previously passed in registers.
When RTL generation is complete, this virtual register is replaced
by the sum of the register given by ARG_POINTER_REGNUM and the
value of FIRST_PARM_OFFSET.
VIRTUAL_STACK_VARS_REGNUM ¶If FRAME_GROWS_DOWNWARD is defined to a nonzero value, this points
to immediately above the first variable on the stack. Otherwise, it points
to the first variable on the stack.
VIRTUAL_STACK_VARS_REGNUM is replaced with the sum of the
register given by FRAME_POINTER_REGNUM and the value
TARGET_STARTING_FRAME_OFFSET.
VIRTUAL_STACK_DYNAMIC_REGNUM ¶This points to the location of dynamically allocated memory on the stack immediately after the stack pointer has been adjusted by the amount of memory desired.
This virtual register is replaced by the sum of the register given by
STACK_POINTER_REGNUM and the value STACK_DYNAMIC_OFFSET.
VIRTUAL_OUTGOING_ARGS_REGNUM ¶This points to the location in the stack at which outgoing arguments
should be written when the stack is pre-pushed (arguments pushed using
push insns should always use STACK_POINTER_REGNUM).
This virtual register is replaced by the sum of the register given by
STACK_POINTER_REGNUM and the value STACK_POINTER_OFFSET.
(subreg:m1 reg:m2 bytenum) ¶subreg expressions are used to refer to a register in a machine
mode other than its natural one, or to refer to one register of
a multi-part reg that actually refers to several registers.
Each pseudo register has a natural mode. If it is necessary to
operate on it in a different mode, the register must be
enclosed in a subreg.
There are currently three supported types for the first operand of a
subreg:
subregs have pseudo
regs as their first operand.
subregs of mem were common in earlier versions of GCC and
are still supported. During the reload pass these are replaced by plain
mems. On machines that do not do instruction scheduling, use of
subregs of mem are still used, but this is no longer
recommended. Such subregs are considered to be
register_operands rather than memory_operands before and
during reload. Because of this, the scheduling passes cannot properly
schedule instructions with subregs of mem, so for machines
that do scheduling, subregs of mem should never be used.
To support this, the combine and recog passes have explicit code to
inhibit the creation of subregs of mem when
INSN_SCHEDULING is defined.
The use of subregs of mem after the reload pass is an area
that is not well understood and should be avoided. There is still some
code in the compiler to support this, but this code has possibly rotted.
This use of subregs is discouraged and will most likely not be
supported in the future.
subregs; such
registers would normally reduce to a single reg rtx. This use of
subregs is discouraged and may not be supported in the future.
subregs of subregs are not supported. Using
simplify_gen_subreg is the recommended way to avoid this problem.
subregs come in two distinct flavors, each having its own
usage and rules:
When m1 is strictly wider than m2, the subreg
expression is called paradoxical. The canonical test for this
class of subreg is:
paradoxical_subreg_p (m1, m2)
Paradoxical subregs can be used as both lvalues and rvalues.
When used as an lvalue, the low-order bits of the source value
are stored in reg and the high-order bits are discarded.
When used as an rvalue, the low-order bits of the subreg are
taken from reg while the high-order bits may or may not be
defined.
The high-order bits of rvalues are defined in the following circumstances:
subregs of mem
When m2 is smaller than a word, the macro LOAD_EXTEND_OP,
can control how the high-order bits are defined.
subreg of regs
The upper bits are defined when SUBREG_PROMOTED_VAR_P is true.
SUBREG_PROMOTED_UNSIGNED_P describes what the upper bits hold.
Such subregs usually represent local variables, register variables
and parameter pseudo variables that have been promoted to a wider mode.
bytenum is always zero for a paradoxical subreg, even on
big-endian targets.
For example, the paradoxical subreg:
(set (subreg:SI (reg:HI x) 0) y)
stores the lower 2 bytes of y in x and discards the upper 2 bytes. A subsequent:
(set z (subreg:SI (reg:HI x) 0))
would set the lower two bytes of z to y and set the upper
two bytes to an unknown value assuming SUBREG_PROMOTED_VAR_P is
false.
When m1 is at least as narrow as m2 the subreg
expression is called normal.
Normal subregs restrict consideration to certain bits of
reg. For this purpose, reg is divided into
individually-addressable blocks in which each block has:
REGMODE_NATURAL_SIZE (m2)
bytes. Usually the value is UNITS_PER_WORD; that is,
most targets usually treat each word of a register as being
independently addressable.
There are two types of normal subreg. If m1 is known
to be no bigger than a block, the subreg refers to the
least-significant part (or lowpart) of one block of reg.
If m1 is known to be larger than a block, the subreg refers
to two or more complete blocks.
When used as an lvalue, subreg is a block-based accessor.
Storing to a subreg modifies all the blocks of reg that
overlap the subreg, but it leaves the other blocks of reg
alone.
When storing to a normal subreg that is smaller than a block,
the other bits of the referenced block are usually left in an undefined
state. This laxity makes it easier to generate efficient code for
such instructions. To represent an instruction that preserves all the
bits outside of those in the subreg, use strict_low_part
or zero_extract around the subreg.
bytenum must identify the offset of the first byte of the
subreg from the start of reg, assuming that reg is
laid out in memory order. The memory order of bytes is defined by
two target macros, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN:
WORDS_BIG_ENDIAN, if set to 1, says that byte number zero is
part of the most significant word; otherwise, it is part of the least
significant word.
BYTES_BIG_ENDIAN, if set to 1, says that byte number zero is
the most significant byte within a word; otherwise, it is the least
significant byte within a word.
On a few targets, FLOAT_WORDS_BIG_ENDIAN disagrees with
WORDS_BIG_ENDIAN. However, most parts of the compiler treat
floating point values as if they had the same endianness as integer
values. This works because they handle them solely as a collection of
integer values, with no particular numerical value. Only real.cc and
the runtime libraries care about FLOAT_WORDS_BIG_ENDIAN.
Thus,
(subreg:HI (reg:SI x) 2)
on a BYTES_BIG_ENDIAN, ‘UNITS_PER_WORD == 4’ target is the same as
(subreg:HI (reg:SI x) 0)
on a little-endian, ‘UNITS_PER_WORD == 4’ target. Both
subregs access the lower two bytes of register x.
Note that the byte offset is a polynomial integer; it may not be a compile-time constant on targets with variable-sized modes. However, the restrictions above mean that there are only a certain set of acceptable offsets for a given combination of m1 and m2. The compiler can always tell which blocks a valid subreg occupies, and whether the subreg is a lowpart of a block.
A MODE_PARTIAL_INT mode behaves as if it were as wide as the
corresponding MODE_INT mode, except that it has a number of
undefined bits, which are determined by the precision of the
mode.
For example, on a little-endian target which defines PSImode
to have a precision of 20 bits:
(subreg:PSI (reg:SI 0) 0)
accesses the low 20 bits of ‘(reg:SI 0)’.
Continuing with a PSImode precision of 20 bits, if we assume
‘REGMODE_NATURAL_SIZE (DImode) <= 4’,
then the following two subregs:
(subreg:PSI (reg:DI 0) 0) (subreg:PSI (reg:DI 0) 4)
represent accesses to the low 20 bits of the two halves of ‘(reg:DI 0)’.
If ‘REGMODE_NATURAL_SIZE (PSImode) <= 2’ then these two subregs:
(subreg:HI (reg:PSI 0) 0) (subreg:HI (reg:PSI 0) 2)
represent independent 2-byte accesses that together span the whole
of ‘(reg:PSI 0)’. Storing to the first subreg does not
affect the value of the second, and vice versa, so the assignment:
(set (subreg:HI (reg:PSI 0) 0) (reg:HI 4))
sets the low 16 bits of ‘(reg:PSI 0)’ to ‘(reg:HI 4)’, and
the high 4 defined bits of ‘(reg:PSI 0)’ retain their
original value. The behavior here is the same as for
normal subregs, when there are no
MODE_PARTIAL_INT modes involved.
The rules above apply to both pseudo regs and hard regs. If the semantics are not correct for particular combinations of m1, m2 and hard reg, the target-specific code must ensure that those combinations are never used. For example:
TARGET_CAN_CHANGE_MODE_CLASS (m2, m1, class)
must be false for every class class that includes reg.
GCC must be able to determine at compile time whether a subreg is
paradoxical, whether it occupies a whole number of blocks, or whether
it is a lowpart of a block. This means that certain combinations of
variable-sized mode are not permitted. For example, if m2
holds n SI values, where n is greater than zero,
it is not possible to form a DI subreg of it; such a
subreg would be paradoxical when n is 1 but not when
n is greater than 1.
The first operand of a subreg expression is customarily accessed
with the SUBREG_REG macro and the second operand is customarily
accessed with the SUBREG_BYTE macro.
It has been several years since a platform in which
BYTES_BIG_ENDIAN not equal to WORDS_BIG_ENDIAN has
been tested. Anyone wishing to support such a platform in the future
may be confronted with code rot.
(scratch:m) ¶This represents a scratch register that will be required for the
execution of a single instruction and not used subsequently. It is
converted into a reg by either the local register allocator or
the reload pass.
scratch is usually present inside a clobber operation
(see Side Effect Expressions).
On some machines, the condition code register is given a register number
and a reg is used.
Other machines store condition codes in general
registers; in such cases a pseudo register should be used.
Some machines, such as the SPARC and RS/6000, have two sets of arithmetic instructions, one that sets and one that does not set the condition code. This is best handled by normally generating the instruction that does not set the condition code, and making a pattern that both performs the arithmetic and sets the condition code register. For examples, search for ‘addcc’ and ‘andcc’ in sparc.md.
(pc) ¶This represents the machine’s program counter. It has no operands and
may not have a machine mode. (pc) may be validly used only in
certain specific contexts in jump instructions.
There is only one expression object of code pc; it is the value
of the variable pc_rtx. Any attempt to create an expression of
code pc will return pc_rtx.
All instructions that do not jump alter the program counter implicitly by incrementing it, but there is no need to mention this in the RTL.
(mem:m addr alias) ¶This RTX represents a reference to main memory at an address represented by the expression addr. m specifies how large a unit of memory is accessed. alias specifies an alias set for the reference. In general two items are in different alias sets if they cannot reference the same memory address.
The construct (mem:BLK (scratch)) is considered to alias all
other memories. Thus it may be used as a memory barrier in epilogue
stack deallocation patterns.
(concatm rtx rtx) ¶This RTX represents the concatenation of two other RTXs. This is used for complex values. It should only appear in the RTL attached to declarations and during RTL generation. It should not appear in the ordinary insn chain.
(concatnm [rtx …]) ¶This RTX represents the concatenation of all the rtx to make a
single value. Like concat, this should only appear in
declarations, and not in the insn chain.